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LT8500
14
8500f
operaTion
PWM CALCULATION BY DIGITAL MULTIPLICATION OF
CORRECTION REGISTER AND PWM UPDATE VALUES
The correction multiplier is used to automatically scale
the 12-bit PWM channel data before storing the PWM
update value for the respective channel. The correction
multiplier is disabled by the correction register disable bit
(CRD),whichistoggledbythecorrectiontogglecommand
(CMD=0x7X). When the correction multiplier is disabled,
the incoming data is stored unchanged:
PWMOUTn = CHANn(NOM)
The correction multiplier is enabled by default (CRD=0)
and scales incoming channel data according to:
PWMOUTn = CHANn (NOM)
2
3
CORn + 32
64
where PWMOUTn is the number of PWMCK cycles that
PWMn is high, CHANn(NOM) is the nth channel field in
the frame, and CORn is the nth programmed correction
setting (CORn = 0 to 63). See Table 1 for examples.
The 6-bit COR value sets a multiplier of 0.5X to ~1.5X
(exactly 1.484375, or ((63 + 32)/64)) with 64 values and
a midrange, signifying a multiple of 1.0, at 32 (0x20). In
order to avoid overflow in the PWM registers when the
multiplier is greater than 1.0, the nominal PWM update
value (CHANn) is first prescaled on chip by 2/3. This
means that the full-scale width for a channel with a mul-
tiplier of 1.0 (CHANn = 4095, CORn = 32) will result in a
PWMOUTn width of 4095 (2/3) 1.0 = 2730, not 4095.
So, a correction multiplier of ~1.5 (CORn = 63) yields a
corrected PWM width of 4052 = 4095 (2/3) 1.484375.
ThePWMOUTnwidthisalwaysroundedtothenearestwhole
number. Table 1 shows examples of PWM calculations for
selected register values. This means the maximum PWM
duty cycle with CRD=0 is 4052/4096, and with CRD=1 it
is 4095/4096.
COMMAND DESCRIPTIONS
The LT8500 implements eight commands, outlined in
Table 2. The commands (CMD) are encoded in the eight
LSB’sofacommandframe,andsoresideintheeightLSB’s
of the shift register when a frame has been completely
shifted in. The command field is executed by the rising
edge of LDI. Only the four MSB’s of the command field
are decoded for commands.
Synchronous Update Frame: CMD = 0x0X
A synchronous update frame updates PWM[48:1] with the
data in the frame, after processing through the Correction
Multiplier. The PWMR is updated when LDIBLANK goes
high. The PWMRSYNC register will be written from the
PWMR synchronously to the start of the PWM period (on
PWMCK 1). This command eliminates shortened PWM
“runt” pulses. The value in the PWMRSYNC registers
will update the PWM outputs on the next rising edge of
PWMCK. Examples are shown in Figure 6, cases B and E.
Table 1. Example PWM Width Calculations (Base 10) with Correction Enabled (CRD = 0)
A
PWM UPDATE VALUE
SENT ON SDI
B
PRESCALED PWM
(A 2/3)
C
CORRECTION REGISTER
(COR) VALUE
D
MULTIPLIER
(C + 32)/64
E
PWM WIDTH (BD)
(IN UNITS OF tPWMCK)
3
2
63
1.484375
3
120
80
63
1.484375
119
120
80
32
1.0
80
120
80
0
0.5
40
1200
800
63
1.484375
1188
1200
800
32
1.0
800
1200
800
0
0.5
400
4095
2730
63
1.484375
4052
4095
2730
32
1.0
2730
4095
2730
0
0.5
1365
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